1. Field of the Invention
The present invention concerns a delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising:                an analog filter for the filtering of the analog input signal,        a quantiser clocked by a clock signal, which contains at least one comparator and quantises the filtered analog signal outputted through the analog filter for the generation of the digital output signal, and        a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one analog feedback signal on the basis of the digital output signal.        
Furthermore the invention concerns a corresponding conversion method.
2. Description of the Prior Art
From DE 10 2004 009 611 A1, for example, a converter of this kind is of known art. In this prior art according to one form of embodiment a quantiser is provided which consists of one comparator and delivers a digital quantiser output signal with one bit resolution. In an alternative form of embodiment the quantiser has a plurality of quantising stages and delivers a digital output signal comprising a plurality of bits. The design and the function of the quantiser are not described in any further detail in this publication.
A fundamental problem with conventional continuous-time delta-sigma analog-digital converters is the so-called offset error of the one or more comparators that are used in the quantiser for the quantisation of the signal supplied. Such a comparator offset error can for example lead to the fact that for an input signal that lies just underneath the comparator threshold, the comparator output signal assumes a value that is stipulated for input signals lying above the comparator threshold. The reverse case is also conceivable. The offset error thus leads ultimately to the fact that under certain circumstances the comparator concerned comes to the incorrect decision. It is clear that this error affects the quality of the delta-sigma analog-digital converter disadvantageously. This problem is particularly serious if the quantiser has a plurality of comparators in order to deliver a comparison result with multiple bit resolution. In this case not only does the offset error of a comparator as such possess relevance for the conversion quality, but so also does the fact that the individual offset errors of the majority of comparators differ from one another in an undefined manner.
A possible option for improvement of the converter quality consists in making the total system less sensitive to offset errors in the region of the quantiser. However this is either linked with a relatively high level of complexity in terms of circuitry or possesses other disadvantages, such as e.g. a reduction of the converter resolution as a result of a reduction of the resolution of the quantiser. Another possible approach for improvement of the converter quality consists in implementing the one or more comparators of the quantiser according to established circuitry concepts using field effect transistors, wherein these transistors are however designed with a particularly large surface area and/or length. This would indeed reduce the offset error of the comparator, but leads to a disadvantageous increase in the power requirement, i.e. current requirement, of the comparator and the upstream part of the circuitry.